3 min readFPGA Development (Using OpenCL)
Hardware acceleration, including graphics processing units (GPUs) and field-programmable gate arrays (FPGAs), has become increasingly popular, with companies like Microsoft accelerating codes that are well-suited for parallel execution. Let’s take a closer look at why FPGAs are so popular, how to improve the development process using OpenCL, and how SoftServe benchmarked using Cyclone V.
WHY FPGA?
FPGAs are treated as promising hardware accelerators for modern AI, ML, and big data solutions, mainly because of their highly parallel nature and ability to process data in-place — substantially reducing processing feedback time and the infrastructure required. Moreover, FPGAs can be thought of as a kind of “soft” hardware, able to be re-tailored for a specific task whenever such a need arises.
Until quite recently, FPGAs were programmed in Verilog and VHDL hardware definition languages. The development process was long and restricted to a relatively small community of hardware engineers. However, the emergence of toolkits is making FPGA programming possible in C/C++. This reduces development time while dramatically increasing the size of the developer community. One such toolkit is Open Compute Language (OpenCL).
OpenCL
Using OpenCL for FPGA programming is a two-stage process:
- Code is written in the OpenCL language (a subset of C).
- The specific toolkit takes the compiled OpenCL code as input to produce the final FPGA image as output.
The first stage essentially mirrors conventional C/C++ programming. The second stage specifically requires a sophisticated tool to load the developed code onto the FPGA. This process is carried out without developer assistance.
FPGA programming using OpenCL is advantageous due to its conventional programming methodology, but keep in mind that learning how to leverage toolkit possibilities takes time. The good news is that the effort is well worth it based on the potential return on investment.
BENCHMARKING WITH CYCLONE V FPGA
Our objective was to solve practical problems using the FPGA SoC. First, the Cyclone V FPGA from Intel was chosen because it is integrated into Terasic’s De10-Nano SoC, which is widely used in university programs — relevant to expanding the FPGA developer community.
SoftServe chose the task of calculating a user’s heart rate based on readings taken only from the forehead region using a laptop’s integrated camera.
Two challenges led to this task selection:
- Porting from a laptop to a much smaller form-factor device (FPGA SoC) and solving an intrinsically non-parallel problem because these are the challenges that FPGAs solve best.
- Initially, FPGA performance lags behind CPU performance. However, we applied several optimization tricks related to programming mathematical operations, as well as general code structure, including:
- Replacing all floating-point operations with fixed-point.
- Replacing multiplications/divisions with additions whenever possible.
- Loop unrolling.
- Optimized data exchange between CPU and FPGA.
Eventually, with FPGA, we successfully achieved 50% faster pure calculations than with a CPU.
CONCLUSION
OpenCL is a promising and powerful tool for programming FPGAs. It substantially reduces FPGA development time and opens FPGA development to a wider community of programmers.
SoftServe helps you streamline hardware acceleration and software optimization to achieve your goals.
Contact us to get started.